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Dajiang Liu
Personal Information
  • Associate Professor
  • Supervisor of Master's Candidates
  • Name (Simplified Chinese):Dajiang Liu
  • Name (Pinyin):liudajiang
  • E-Mail:
  • Date of Employment:2017-09-15
  • School/Department:计算机学院
  • Education Level:Postgraduate (Postdoctoral)
  • Business Address:A区主教学楼
  • Gender:Male
  • Contact Information:liudj@cqu.edu.cn
  • Degree:Doctoral Degree in Engineering
  • Professional Title:Associate Professor
  • Status:Employed
  • Alma Mater:清华大学
Other contact Information
Profile

刘大江,博士,重庆大学计算机学院副教授、硕士生导师;2009年本科毕业于电子科技大学微电子技术专业;同年9月进入清华大学微纳电子系直接攻读博士学位,2015年获得工学博士学位;同年8月进入清华大学计算机系进行博士后研究,2017年出站;同年9月进入重庆大学计算机学院工作至今,现为重庆大学计算机学院副教授,于2018年在澳大利亚昆士兰大学和悉尼科技大学进行访问交流。研究领域包括可重构计算架构及编译优化、图计算硬件加速器和三维场景表示加速器;曾主持和参与了国家自然科学基金、科技创新2030-新一代人工智能、华为高校合作技术合作和CCF-腾讯犀牛鸟基金等多个项目;在DAC、ICCAD、DATE、TCAD、TVLSI等重要国际会议和期刊发表十余篇论文;现为IEEE和中国计算机协会会员;曾获教育部科技成果完成者证书。


部分论文:

  1. D. Liu*, Y. Xia, J. Shang, J. Zhong, S. Yin. E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping, IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, pp.46-60. (CCF-A)

  2. D. Liu*, D. Pan, X. Xiong, J. Shang, S. Yin. PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis, ACM/EDAC/IEEE Design Automation Conference (DAC), 2024, pp. 1-6. (CCF-A)

  3. Y. Liang, D. Mou, D. Liu*, DISC: Exploiting Data Parallelism of Non-Stencil Computations on CGRAs via Dynamic Iteration Scheduling, 2024 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024, pp. 1-9. (CCF-B, To appear.)

  4. X. Mo, Y. Li, D. Liu*, Optimizing Imperfectly-Nested Loop Mapping on CGRAs via Polyhedral-Guided Flattening, 2024 Design, Automation and Test in Europe Conference (DATE), 2024, pp. 1-6. (CCF-B)

  5. D. Liu*, D. Mou,R. Zhu,J. Shang,J. Zhong, S. Yin*. DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs, ACM/EDAC/IEEE Design Automation Conference (DAC), 2023, pp. 1-6.  (CCF-A)

  6. L. Huang,D. Liu*. Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations, ACM/EDAC/IEEE Design Automation Conference (DAC), 2023, pp. 1-6. (CCF-A)

  7. D. Liu*, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng, S. Zhou. Data-Flow Graph Mapping Optimization for CGRA with Deep Reinforcement Learning, IEEE Trans. on Computer-Aided Design (TCAD) of Integrated Circuits and Systems,2019,38(12):2271-2283. (CCF-A)

  8. Y. Zhuang, Z. Zhang, D. Liu*. Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning, 2022 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022, pp. 1-9. (CCF-B)

  9. D. Liu*, T. Liu, X. Mo, J. Shang, J. Zhong, S. Yin. Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs, 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021, pp. 1-9. (CCF-B)

  10.  B. Wang, R. Zhu, J. Shang, D. Liu*, Towards Energy-Efficient CGRAs via Stochastic Computing[C], 2022 Design, Automation and Test in Europe Conference (DATE), 2022, pp. 1-6. (CCF-B)



Social Affiliations

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Education Background
Work Experience
  • 2009-
    2015
    清华大学 | 电子科学与技术 | With Certificate of Graduation for Doctorate Study
  • 2005-
    2009
    电子科技大学 | 微电子与固体电子 | University graduated
  •  重庆大学 
  •  清华大学 
Research Group

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